There are many situations wherein the clock source employed in an electrical system requires to be switched to another clock source. For example, during maintenance operations, it may become necessary to disconnect the module that contains a clock source from the rest of a system that employs the signals generated from that clock source. In order to prevent any interruption in the operation of the rest of the system, a standby clock source is employed so as to provide the necessary clock signals.
Typically, the frequency of the signals generated by the original clock source is the same as the frequency of the signals generated by the standby clock source. However, most of the time, the phase of the two clock sources are different. A substantial phase difference between the two clock sources may lead to unacceptable data loss and errors when the first clock source is switched with the standby clock source.
FIG. 1 illustrates a prior art system employed to alleviate the consequences of such switching errors. A low bandwidth phase-locked loop is employed to receive the signals provided by the selected clock source and the standby clock source. Thus, FIG. 1 illustrates a system 10 that operates based on clock signals such as electrical pulses generated by clock source 14 or standby clock source 16. The output port of clock source 14 is coupled to an input port of a low bandwidth phase-locked loop 12 via a switch 18. Furthermore, the output port of phase locked-loop 12 is coupled to an input port of system 10. During operation, system 10 receives its clock signals from clock source 14 via phase-locked-loop 12 which generates clock signals that are substantially in-phase with the signals generated by clock source 14.
Once it is desired to operate system 10 from standby clock source 16, switch 18 is activated to connect the output port of clock 16 to the input port of phase-locked-loop 12. The frequency of the signals generated by standby clock source 16 is substantially the same as the frequency of the signals generated by clock source 14. However, the phase of the signals may be different and misaligned. One of the purposes to employ phase-locked-loop 12 is to smoothen the effect of the phase jump caused by the standby clock source 16, as seen by system 10.
Phase-locked-loop 12 functions as a low pass filter in the phase domain. To this end the phase of signals generated at the output port of phase-locked-loop 12 gradually change until it is substantially aligned with the phase of the signals generated by standby clock source 16. It is noted that the rate of change of the phase of the signals at the output port of the phase-locked-loop, among other things depends on the bandwidth of the system. Thus, the lower the bandwidth of the phase-locked-loop the slower the rate of change of the phase of the signals. As a result, it is desirable to design the phase-locked-loop so that it exhibits a substantially low bandwidth. Consequently, the transition of the phase of the signals at the output of the phase-locked loop from one phase relating to clock source 14 to a second phase relating to clock source 16 may appear seamless, leading to substantially low data error rates.
A problem with the arrangement illustrated in FIG. 1 is that low bandwidth phase-locked-loops, particularly those employing CMOS technology, exhibit unacceptable jitter signals as the bandwidth decreases. This jitter is typically originated from thermal and flicker noise associated with the operation of a monolithic ring oscillator employed in the phase-locked-loop. One way to overcome this problem is to employ a voltage-controlled crystal oscillator. This solution provides acceptable jitter characteristics. However, this solution is not amenable to integrated circuit manufacturing. Furthermore, it leads to higher manufacturing costs.
Thus, there is a need for a system that aligns the phase of the output clock signals generated from a standby clock source with the phase of the signals generated by an active clock source when the clock sources are switched.